The invention is directed to an improved approach for implementing prototyping and analysis of electronic circuit designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools.
The EDA tools may be used to perform early stage analysis and examinations of an electronic design. For example, the EDA tools may be used to determine whether the electronic design is capable of meeting timing requirements along signal paths in the design. Failure of a design to adequately meet timing requirements could result in an electronic product that may fail under usage and/or not function according to its intended purpose. Therefore, for design and planning purposes, it is very desirable for engineers and designers to be able to obtain an early-stage estimate of the likelihood that a particular design will meet its timing requirements. Early identification of timing problems allows the designer to address the timing identified issues in a much more efficient way than if such timing problems are discovered later in the design cycle.
One possible approach to address this problem of early timing analysis is to employ a pure top-down timing budget analysis. In this approach, prototyping or modeling of the circuit design is used to perform timing analysis on the circuit, in which budgeting and partitioning of the circuit is performed in a top-down manner such that each portion of logic is given a specified percentage/portion of the virtual timing budget based upon a top-down guess and/or expected need regarding the timing needs for each logic portion. Block and full chip implementations would then occur to perform analysis of the timing results, with the process looping back to the budgeting and partitioning steps once it is discovered that the earlier budgeting/partitioning corresponds to expected timing problems. This cycle repeats itself until the expected timing results meets the requirements fro the designer. One problem with this approach is that conventional modeling and prototyping techniques causes this process to take an excessive amount of time and computing resources, particularly given the large number of objects and features that exist on modern electronic designs. In addition, conventional top-down modeling and prototyping approaches can fail to identify timing errors at an early stage of the design cycle, such that timing problems are only identified once the analysis has returned to the top level. This can be caused, in part, by unrealistic time budgeting that is imposed during the modeling and analysis process.
Therefore, there is a need for an improved approach to implement prototyping and/or modeling for electronic designs that allows for efficient analysis of the electronic designs. There is also a need for an improved and more efficient approach to perform early-stage timing analysis upon the electronic designs.